Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). The transistors can include gate stacks or structures disposed between drain and source regions. The gate structure typically includes a conductive layer that has a rectangular cross-section and a dielectric or gate oxide layer. The conductive layer is disposed over the dielectric layer. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the dielectric layer of the gate stack to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects, which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
As transistors disposed on integrated circuits (ICs) become smaller (e.g., transistors with gate lengths approaching 50 nm), transistors become more susceptible to gate-edge fringing field effects. A fringing electrical field exists near the edges of the gate stack of transistors, such as, MOSFETS. The fringing electrical field has negative effects on transistor performance. For example, the fringing field can produce a fringing overlap capacitance that is non-zero even when an overlap does not exist between the gate and the source/drain region (i.e., the gate stack and the source/drain extensions).
Generally, conventional gate dielectric materials, such as, silicon dioxide, are less applicable as transistor size is decreased. For example, gate dielectrics consisting of silicon dioxide can be subject to high leakage current caused by "direct tunneling effect." As channel lengths approach 50 nm or less, high dielectric constant (k) dielectric materials must replace medium to low-k materials (e.g., k&lt;8.0) as the gate dielectric layer. Silicon dioxide has a k value of approximately 3.9.
For advanced ULSI MOS transistors, high dielectric constant (k) material, such as, titanium dioxide (TiO.sub.2), or tantalum pentaoxide (Ta.sub.2 O.sub.5), can be used as a gate insulator or a dielectric layer to suppress tunneling leakage current. In MOSFETs with high-k (k&gt;25) gate dielectric materials, the fringing field effect near the gate stack is more significant than conventional MOSFETs, which utilize a medium or low-k dielectric material, such as, silicon dioxide. Accordingly, transistors with high-k dielectric materials are more susceptible to gate-edge fringing field effects. In small transistors, the contribution of the fringing capacitance to the total overlap capacitance can be extremely significant (e.g., more than 50 percent). The gate-edge fringing field effect can even adversely affect the ability of the gate conductor to couple to the channel and to the source/drain extensions. The gate-edge fringing field effect can also degrade the control of charges in the channel by the gate stack, thereby degrading subthreshold characteristics of the transistor.
Thus, there is a need for a MOSFET transistor that is less susceptible to gate-edge fringing field effects. Further still, there is a need for a MOSFET that includes a high-k gate dielectric material. Further still, there is a need for an efficient method of manufacturing a MOSFET that has suppressed gate-edge fringing field effects.